http://open-source-security-software.net/project/zydis/releases.atom 2025-07-07T08:58:19.406779+00:00 python-feedgen zydis v2.0.0-beta1 2017-12-12T14:31:36+00:00 This is the first beta release, the public interface is now expected to be stable. ## Detailed changelog (since v2.0.0-alpha2) - Added new ISA-extensions - `BITALG` - `GFNI` - `RDPID` - `VAES` - `VBMI2` - `VNNI` - `VPCLMULQDQ` - Added implicit operands for instructions with stack-operations - Implicit `SP/ESP/RSP` register-operand - Implicit `[SP/ESP/RSP]` memory-operand - Implemented decoder-modes to support ISA-extensions that conflict with existing instructions - Added decoder-modes - `ZYDIS_DECODER_MODE_MINIMAL` - `ZYDIS_DECODER_MODE_AMD_BRANCHES` - `ZYDIS_DECODER_MODE_KNC` - `ZYDIS_DECODER_MODE_MPX` - `ZYDIS_DECODER_MODE_CET` - `ZYDIS_DECODER_MODE_LZCNT` - `ZYDIS_DECODER_MODE_TZCNT` - Removed `ZydisDecoderInitEx` and the possibility to pass a decoder-granularity (use `ZYDIS_DECODER_MODE_MINIMAL` instead) - Decoder improvements - Instructions which are only valid in protected-mode are now rejected, if `ZYDIS_MACHINE_MODE_REAL_16` is used - The `scale` of memory-operands is now correctly set to `1` in 16-bit mode, if an index register was specified - Major formatter changes - Switched to custom length-aware `ZydisString` "class" to improve performance and usability - Added `ZydisFormatterSetAttribute` function for simple formatter customization - `ZYDIS_FORMATTER_PROP_UPPERCASE` - `ZYDIS_FORMATTER_PROP_FORCE_MEMSEG` - `ZYDIS_FORMATTER_PROP_FORCE_MEMSIZE` - `ZYDIS_FORMATTER_PROP_ADDR_FORMAT` - `ZYDIS_FORMATTER_PROP_DISP_FORMAT` - `ZYDIS_FORMATTER_PROP_IMM_FORMAT` - `ZYDIS_FORMATTER_PROP_HEX_UPPERCASE` - `ZYDIS_FORMATTER_PROP_HEX_PREFIX` - `ZYDIS_FORMATTER_PROP_HEX_SUFFIX` - `ZYDIS_FORMATTER_PROP_HEX_PADDING_ADDR` - `ZYDIS_FORMATTER_PROP_HEX_PADDING_DISP` - `ZYDIS_FORMATTER_PROP_HEX_PADDING_IMM` - Hook refactorings - Added `ZYDIS_FORMATTER_HOOK_PRE_OPERAND`, `ZYDIS_FORMATTER_HOOK_POST_OPERAND` and `ZYDIS_FORMATTER_HOOK_PRINT_REGISTER` - Renamed `ZYDIS_FORMATTER_HOOK_PRINT_DISPLACEMENT` to `ZYDIS_FORMATTER_HOOK_PRINT_DISP` - Renamed `ZYDIS_FORMATTER_HOOK_PRINT_IMMEDIATE` to `ZYDIS_FORMATTER_HOOK_PRINT_IMM` - Renamed `ZYDIS_FORMATTER_HOOK_PRINT_OPERANDSIZE` to `ZYDIS_FORMATTER_HOOK_PRINT_MEMSIZE` - Removed `ZYDIS_FORMATTER_HOOK_PRINT_SEGMENT` - Improved no-libc support - Added `ZYDIS_NO_LIBC` CMake switch - When enabled, removes dependency on `memset`, `memcpy` and `strlen` - Added custom integer types - Added own `NULL` - Added project logo - Contributed by [LekoArts](https://github.com/LekoArts) - Added Visual Studio project files - Static-, shared- and kernel-mode configuration - Contributed by [Mattiwatti](https://github.com/Mattiwatti) 2017-12-12T14:31:36+00:00 zydis v2.0.0 2018-03-01T16:09:23+00:00 This is the final release of Zydis 2. ## Detailed changelog (since v2.0.0-beta1) - Improved instruction decoding - Fixed decoding of `XOP` instructions - Fixed handling of illegal `LOCK` prefixes for `XOP/VEX/EVEX/MVEX` instructions - Significantly improved detection of bad register values - Added check for invalid `GATHER` registers - Fixed `EVEX/MVEX.R'` not beeing ignored in 16- and 32-bit mode - Improved formatter - Omitting an operand by using formatter hooks will now correctly omit the semicolon as well - `ZYDIS_FORMATTER_HOOK_PRE_OPERAND` and `ZYDIS_FORMATTER_HOOK_POST_OPERAND` can now be used to omit a specific operand - Added `ZydisFormatterFormatOperand` and `ZydisFormatterFormatOperandEx` (this won't print AVX-512/KNC decorators) - User defined callbacks should return `ZYDIS_STATUS_SKIP_OPERAND` to omit an operand (returning `ZYDIS_STATUS_SUCCESS` without writing to the buffer is now deprecated) - Added new instructions - `PCONFIG` - `EXTRQ`, `INSERTQ`, `MOVNTSD`, `MOVNTSS` (SSE4a) - `MONITORX`, `MWAITX` - `ENCLV` - `VPOPCNTD`/`VPOPCNTQ` instructions with 128- and 256-bit vector-length - Added missing `VEX`-encoded `GFNI` instructions - Fixed some instruction definitions - Changed `XSAVE`/`XSAVEOPT` memory operand from W to RW - Changed amount of bytes popped from stack by the `IRET` instruction - Fixed `LWPINS` and `LWPVAL` instructions - Fixed exception-class of some `GFNI` instructions - Fixed `RDRAND` and `RDSEED` instructions - Fixed `SYSRET` instruction - Fixed `XCHG R8, RAX` falsely beeing decoded as `NOP` - Fixed operand size of some conditional jump instructions - Changed destination operand action of `PEXT`, `PDEP` and `ANDN` from read/write to write-only - Misc bugfixes - Fixed formatting of memory operands with explicit segment register - Fixed a bug in `ZydisRegisterGetClass` that caused the function to report invalid register-classes for `IP` and `FLAGS` registers - Changed type of implicit memory operands to `ZYDIS_MEMOP_TYPE_MEM` instead of `ZYDIS_MEMOP_TYPE_INVALID` 2018-03-01T16:09:23+00:00 zydis v2.0.1 2018-05-05T13:29:41+00:00 ## Detailed changelog (since v2.0.0 Final) - Improved instruction decoding - Fixed decoding of `IS4` encoded operands in non 64-bit mode - Fixed check for invalid gather registers in non 64-bit mode - Improved formatter - Fixed padding of immediate values - Fixed printing of `XACQUIRE`/`XRELEASE` prefixes (formatter) - Fixed some instruction definitions - `SCAS`, `INS` and `STOS` does not allow the default `ES` segment to be overridden with a segment override prefix - Renamed `SAVESSP` to `SAVEPREVSSP` - Fixed `ENCLS`, `ENCLU` and `ENCLV` instructions - Misc bugfixes - Added missing `extern "C"` block in `String.h` - Changed type of `MOFFS` memory operands to `ZYDIS_MEMOP_TYPE_MEM` instead of `ZYDIS_MEMOP_TYPE_INVALID` 2018-05-05T13:29:41+00:00 zydis v2.0.2 2018-07-22T14:36:27+00:00 - Fixed build on CentOS / RHEL - or, more generally speaking, any toolkit that doesn't enable C99 support by default - Fixed gather register check for `VGATHERPF0{D|Q}{PS|PD}` instruction - Fixed check for invalid BOUND registers - Fixed printing of hex-suffix for `0` values - Fixed CPU-flag actions for instructions that `TEST` and `MODIFIY` certain flags at the same time - Introduced a new CPU-flag action called `TESTED_MODIFIED` - Some FreeBSD fixes for examples and including Zydis in shared/static libraries (contributed by @gdbinit) - Fixed two wrong assert conditions 2018-07-22T14:36:27+00:00 zydis v2.0.3 2019-03-05T12:17:30+00:00 - Fixed various smaller bugs - Fixed CMake install rules to correctly install `ZydisInfo` and `ZydisDisasm` as intended 2019-03-05T12:17:30+00:00 zydis v3.0.0 2019-10-02T13:02:44+00:00 ## Detailed changelog (since v2.0.3) ### Decoder - Improved legacy prefix decoding - Fixed gather register check for `VGATHERPF0{D|Q}{PS|PD}` instruction - Fixed some incorrect assert conditions - Fixed check for invalid `BOUND` registers - Fixed incorrect value of `ZydisDecodedInstruction.raw.prefixes[n].type` in some edge cases ### Formatter - Implemented `AT&T` formatter-style - Implemented `MASM` formatter-style - Implemented tokenization feature to the instruction - `ZydisFormatterTokenizeInstruction`/`ZydisFormatterTokenizeInstructionEx` and `ZydisFormatterTokenizeOperand`/`ZydisFormatterTokenizeOperandEx` generates a token-list instead of a simple string - Each token has a type (like `MNEMONIC`, `REGISTER`, `DELIMITER`) and contains a string - Tokenization allows users to receive the formatted instructions as a stream of tokens with annotations of their purpose, allowing for easier implementation of features such as syntax highlighting - Numeric base (decimal, hexadecimal), signedness and padding can now be independently configured for all numeric types (addresses, displacements and immediates) - Added "detailed prefixes" mode - Prints all instruction prefixes instead of only the effective ones - Replaced the `ZYDIS_FORMATTER_PROP_UPPERCASE` property with more granular options - Allows configuration of the letter-case individually for `prefixes`, `mnemonics`, `registers`, `typecasts` and `decorators` - Implemented more formatter options - `ZYDIS_FORMATTER_PROP_FORCE_RELATIVE_BRANCHES` - Prints relative addresses instead of absolute ones for branch instructions - `ZYDIS_FORMATTER_PROP_FORCE_RELATIVE_RIPREL` - Prints relative addresses instead of absolute ones for `EIP/RIP`-relative instructions - `ZYDIS_FORMATTER_PROP_PRINT_BRANCH_SIZE` - Prints the size of branch instructions (`short`/`near`) ### Database - Added `BF16` instructions - Added `vp2intersect{d|q}` instructions - Added `enqcmd` and `enqcmds` instructions - Added AMD `rdpru` instruction - Added `PADLOCK` instructions - Added `CLDEMOTE`, `MOVDIR` and `WAITPKG` extensions - Added implicit `PKRU` register to the `RDPKRU`/`WRPKRU` instructions - Fixed exception-class of `v4fmaddss`, `v4fnmaddss` and `vcvtps2ph` - Fixed `KNL` gather/scatter memory operand width - Fixed mask-mode for some EVEX instructions - Fixed element size of `VP4DPWSSDS` memory operand - Fixed `MONITOR`, `MONITORX`, `MWAIT` and `MWAITX` operands - Fixed `CLRSSBSY` memory operand is read-write - Fixed `VMREAD` destination operand is write-only - Fixed decoding of `nop` (`0F 1C`) with `66` prefix - Fixed decoding of `rdrand` and `rdseed` with `66` prefix - Fixed decoding of `xstore` with `66` prefix - Adjusted element-type for auto generated `FLAGS/EFLAGS/RFLAGS` and `X87STATUS` operands - Updated `movsxd` source register width - Introduced a new element-type for condition-codes - This allows generic detection of condition-code operands without hardcoding any instruction mnemonics (e.g. used by `CMPPS`, `VCMPPD`, ...) - Added support for non-default address-size configurations - Some instructions (e.g. `ENCLS` or `BNDCL`) are using non-default address-size configurations like ignoring the address-size override prefix or forcing the address size to certain values - Use `MODRM_RM` instead of `MODRM_REG` for the destination register of `EXTRQ` - Removed `W0` filter from `LLWPCB`/`SLWPCB` (is allowed to have 64-bit operand-size) - Added new attributes for instructions that access CPU/FPU/XMM state - `ZYDIS_ATTRIB_CPU_STATE_{CR|CW}` for general CPU-state access - `ZYDIS_ATTRIB_FPU_STATE_{CR|CW}` for FPU-state (x87 and MMX) access - `ZYDIS_ATTRIB_XMM_STATE_{CR|CW}` for XMM-state access - Fixed CPU-flag actions for instructions that `TEST` and `MODIFIY` certain flags at the same time - Introduced a new CPU-flag action called `TESTED_MODIFIED` - Added `ZYDIS_ATTRIB_CPU_STATE_{CR|CW}` attribute to `iret{d|q}` - Added implicit writes for the `CS` and `SS` registers to `syscall` and `sysret` ### Misc - Implemented color support (VT100) and syntax highlighting for the `ZydisInfo` tool - Added `ZydisGetInstructionSegments` helper function - Returns a list that maps the different instruction segments (like `OPCODE`, `MODRM`, ...) to an offset-size pair - The `ZydisInfo` tool now prints the hexadecimal instruction bytes using different colors considering the instruction segment - Added `ZydisCalcAbsoluteAddressEx` which takes an additional register-context argument to allow calculation of addresses depending on runtime register values - Introduced `ZYDIS_MINIMAL_MODE` CMake option - Forces `ZYDIS_DECODER_MODE_MINIMAL` - Reduces file size by excluding unused code and data-tables - Improved MSVC project 2019-10-02T13:02:44+00:00 zydis v3.1.0 2020-02-24T15:31:31+00:00 ## Changes since v3.0.0 ### Enhancements - Allow zycore dependency path to be changed via CMake variable - Added build support for Solaris OS (contributed by @psumbera) ### Fixes - Fixed MinGW builds - Fixed compilation with ICC running in MSVC emulation mode - Various decoder fixes - Classify `LOOP/LOOPE/LOOPNE` as `short-branch` (#126) - Fixed implicit IP operand for short jcc in long mode (#133) - Ignore `EVEX.B` for `vcvtsi2sd`/`vcvtusi2sd` `EVEX.W = 0` forms (#133) - Ignore `REX.X` for `RM`-encoded `BND` registers (#133) - Correctly handle relative memory addressing not being allowed for `MIB` operands (e.g. `bndldx`/`bndstx`) (#133) 2020-02-24T15:31:31+00:00 zydis v3.2.0 2021-10-31T17:34:14+00:00 ## Detailed changelog (since v3.1.0) **Note:** This was already published previously. If you just got a second notification for this, it's because something went wrong when placing the original tag on the right commit, and the corresponding release was deleted by GitHub when the tag was adjusted. No action is required and if you previously pulled from the old tag, you still have the latest released code. Sorry for the inconvenience! ### Decoder - Added `flags_read` and `flags_written` masks to `ZydisDecodedInstruction` for more intuitive and performant access - Added support for `4FMAPS` multisource operands - Added support for `CET` no-track prefix - Fixed Load-op SwizzUpConv(F32) - Fixed wrong eviction hint formatter-string - Fixed `MVEX` rounding mode decoding - Improved handling of 16-bit relative operands - Improved general segment override handling - `XOP`/`VEX`/`EVEX` is invalid in 16-bit real mode - Scale base register of implicit `SP`/`BP` memory operands by stack- instead of address-size - Set `ZYDIS_ATTRIB_ACCEPTS_SEGMENT` for non legacy instructions ### Formatter - Added formatter option to control printing of scale `*1` - Fixed relative disp printing for 0 disps - Fixed incorrect formatting of signed displacements - Fixed formatting of offset for `PTR` operands - Fixed `{sae}`/`{rc}` formatting - Enhanced formatting for `MIB` operands - Print missing `{z}` decorator for instructions with control-masking - Print asterisk in front of absolute `jmp`/`call` address (AT&T) ### Database - Added AVX-512 `FP16` instructions - Added `VNNI` instructions - Added `HRESET` instructions - Added `KEYLOCKER` instructions - Added `TDX` instructions - Added AMD `INVLPGB` instructions - Added AMD `mcommit` instruction - Added `SERIALIZE` and `TSX-LDTRK` instructions - Added AMD `SNP` instructions - Added `AMX` instructions - Added missing conditional-write registers for STOS{B|W|D|Q} and `LODS{B|W|D|Q}` - Fixed privilege level of CET instructions - Fixed decoding of RDSSPD in 64-bit mode - Fixed segment register for `leave` instruction - Fixed `invlpga` and `pvalidate` pseudo memory operand register width - Fixed `bsf`/`bsr` destination operand action - Fixed `DI`/`SI` operand access action for `stos{b|w|d|q}`/`movs{b|w|d|q}` instructions - Fixed `CET`/`VMX` decoding in real mode - Fixed `ECX` scaling for `pcmpestri`/`vpcmpestri`/`pcmpistri`/`vpcmpistri` - Set fixed vector-length for EVEX instructions that ignore EVEX.LL (LIG) - Removed impossible `jcxz`/`jrcxz` encodings - Ignore segment override for memory operands with hardcoded `ES` segment - Ignore segment override for `BNDC{L|N|U}` - Display implicit pseudo memory operand for `vmrun` and `vmsave` - Allow `invlpgb` with 16-bit address-size - Change branch-type from `short` -> `near` for `jkzd`/`jknzd` ### Misc - Improve `CMake` files - Fix buffer overflow and off-by-one in `ZydisInfo` tool 2021-10-31T17:34:14+00:00 zydis v3.2.1 2021-11-08T21:33:30+00:00 ## Detailed changelog (since v3.2.0) This is a security update. ### Formatter - CVE-2021-41253: [Fixed a bug where an internal formatter structure wasn't properly initialized.](https://github.com/zyantific/zydis/commit/330b259583ade789886ce11af2ebcd030097dcbf) - For users that extend the formatter via the formatter hook mechanism and use the string functions provided in zycore to append untrusted data to the formatter buffer, this can result in heap memory corruption. If you don't extend the formatter, this bug doesn't affect you. - For more details, please consult our [security advisory](https://github.com/zyantific/zydis/security/advisories/GHSA-q42v-hv86-3m4g). - Thanks to [@geeknik](https://github.com/geeknik) who found this issues during fuzzing, providing us with a test case for reproducing it! This version is both API and ABI compatible with `v3.2.0`. 2021-11-08T21:33:30+00:00 zydis v4.0.0-rc.1 2022-10-09T20:36:23+00:00 - Added encoding functionality, allowing users to use Zydis for code generation and rewriting - A **huge** thanks goes to @mappzor, who contributed pretty much the entire implementation by himself - Split instruction and operand decoding, allowing users to decode only the data they actually need - Added support for creating amalgamized builds, essentially combining all of Zydis and the required Zycore source code files and headers into a single header and source file, greatly simplifying linking against Zydis on the quick - Improved and automatically built [documentation for all recent versions of Zydis](https://doc.zydis.re/) - Added maximally simplified all-in-one disassembler function (see [#379](https://github.com/zyantific/zydis/pull/379) for details) ## Porting Guide We offer a [porting guide](https://github.com/zyantific/zydis/blob/master/assets/porting-guide-v3-v4.md) for the breaking changes from `v3` to `v4`. ## Important Changes ### Decoder * Fix general address-width handling by @flobernd in [#238](https://github.com/zyantific/zydis/pull/238) * Fix register constraints of certain `AMX` instructions by @flobernd in [#271](https://github.com/zyantific/zydis/pull/271) * Fixed constraint enforcement for AMX instructions by @mappzor in [#276](https://github.com/zyantific/zydis/pull/276) * Decouple operand decoding by @flobernd in [#278](https://github.com/zyantific/zydis/pull/278) * Remove deprecated `accessed_flags` flags field from `ZydisDecodedInstruction` by @flobernd in [#262](https://github.com/zyantific/zydis/pull/262) * Add unions in decoded instruction and operands by @athre0z in [#326](https://github.com/zyantific/zydis/pull/326) * Declare structs as anonymous within anonymous unions by @ZehMatt in [#329](https://github.com/zyantific/zydis/pull/329) * Change `st0` operand visibility as specified by SDM by @athre0z in [#331](https://github.com/zyantific/zydis/pull/331) * Improved signedness data accuracy and consistency (Fixes #327) by @mappzor in [#336](https://github.com/zyantific/zydis/pull/336) ### Encoder * Implemented instruction encoder by @mappzor in [#254](https://github.com/zyantific/zydis/pull/254) * Added `ZydisEncoderNopFill` by @mappzor in [#376](https://github.com/zyantific/zydis/pull/376) * Added function to calculate and encode relative operands by @mappzor in [#368](https://github.com/zyantific/zydis/pull/368) ### Build * Add option to use system installed Zycore by @Tachi107 in [#250](https://github.com/zyantific/zydis/pull/250) * Fix build on macOS 12 by @athre0z in [#259](https://github.com/zyantific/zydis/pull/259) * Get rid of ZydisExportConfig.h by @athre0z in [#301](https://github.com/zyantific/zydis/pull/301) * Add script for generating an amalgamated distribution by @athre0z in [#302](https://github.com/zyantific/zydis/pull/302) * Add WebAssembly support by @williballenthin in [#277](https://github.com/zyantific/zydis/pull/277) * Improve LTO support by @athre0z in [#333](https://github.com/zyantific/zydis/pull/333) * Add Makefile for quick access to various operations by @athre0z in [#346](https://github.com/zyantific/zydis/pull/346) ### Misc * Utils: remove ZydisPE by @athre0z in [#257](https://github.com/zyantific/zydis/pull/257) * Docs: add man pages by @Tachi107 in [#267](https://github.com/zyantific/zydis/pull/267) * Registers: add lookup tables for `ZydisRegister` and `ZydisRegisterClass` by @flobernd in [#283](https://github.com/zyantific/zydis/pull/283) * Tools: improve `ZydisInfo` by @flobernd in [#285](https://github.com/zyantific/zydis/pull/285) * Formatter: fix `MASM` style disassembly by @flobernd in [#298](https://github.com/zyantific/zydis/pull/298) * Segments: move segment functions into a separate, optional header by @athre0z in [#348](https://github.com/zyantific/zydis/pull/348) * Formatter: simplify formatter interface by @athre0z in [#361](https://github.com/zyantific/zydis/pull/361) * Doc: switch Doxygen theme by @athre0z in [#373](https://github.com/zyantific/zydis/pull/373) * CI: add automated documentation builds by @athre0z in [#374](https://github.com/zyantific/zydis/pull/374) **Full Changelog**: https://github.com/zyantific/zydis/compare/v3.2.1...v4.0.0 2022-10-09T20:36:23+00:00 zydis v4.0.0 2022-11-20T17:10:10+00:00 - Added encoding functionality, allowing users to use Zydis for code generation and rewriting - A **huge** thanks goes to @mappzor, who contributed pretty much the entire implementation by himself - Split instruction and operand decoding, allowing users to decode only the data they actually need - Added support for creating amalgamized builds, essentially combining all of Zydis and the required Zycore source code files and headers into a single header and source file, greatly simplifying linking against Zydis on the quick - Improved and automatically built [documentation for all recent versions of Zydis](https://doc.zydis.re/) - Added maximally simplified all-in-one disassembler function (see [#379](https://github.com/zyantific/zydis/pull/379) for details) Check out our [corresponding blog article](https://zyantific.com/posts/zydis-v4-0-released/) for details and examples! ## Porting Guide We offer a [porting guide](https://github.com/zyantific/zydis/blob/master/assets/porting-guide-v3-v4.md) for the breaking changes from `v3` to `v4`. ## Important Changes ### Decoder * Fix general address-width handling by @flobernd in [#238](https://github.com/zyantific/zydis/pull/238) * Fix register constraints of certain `AMX` instructions by @flobernd in [#271](https://github.com/zyantific/zydis/pull/271) * Fixed constraint enforcement for AMX instructions by @mappzor in [#276](https://github.com/zyantific/zydis/pull/276) * Decouple operand decoding by @flobernd in [#278](https://github.com/zyantific/zydis/pull/278) * Remove deprecated `accessed_flags` flags field from `ZydisDecodedInstruction` by @flobernd in [#262](https://github.com/zyantific/zydis/pull/262) * Add unions in decoded instruction and operands by @athre0z in [#326](https://github.com/zyantific/zydis/pull/326) * Declare structs as anonymous within anonymous unions by @ZehMatt in [#329](https://github.com/zyantific/zydis/pull/329) * Change `st0` operand visibility as specified by SDM by @athre0z in [#331](https://github.com/zyantific/zydis/pull/331) * Improved signedness data accuracy and consistency (Fixes #327) by @mappzor in [#336](https://github.com/zyantific/zydis/pull/336) ### Encoder * Implemented instruction encoder by @mappzor in [#254](https://github.com/zyantific/zydis/pull/254) * Added `ZydisEncoderNopFill` by @mappzor in [#376](https://github.com/zyantific/zydis/pull/376) * Added function to calculate and encode relative operands by @mappzor in [#368](https://github.com/zyantific/zydis/pull/368) ### Build * Add option to use system installed Zycore by @Tachi107 in [#250](https://github.com/zyantific/zydis/pull/250) * Fix build on macOS 12 by @athre0z in [#259](https://github.com/zyantific/zydis/pull/259) * Get rid of ZydisExportConfig.h by @athre0z in [#301](https://github.com/zyantific/zydis/pull/301) * Add script for generating an amalgamated distribution by @athre0z in [#302](https://github.com/zyantific/zydis/pull/302) * Add WebAssembly support by @williballenthin in [#277](https://github.com/zyantific/zydis/pull/277) * Improve LTO support by @athre0z in [#333](https://github.com/zyantific/zydis/pull/333) * Add Makefile for quick access to various operations by @athre0z in [#346](https://github.com/zyantific/zydis/pull/346) ### Misc * Zycore: updated to v1.4.1 * Utils: remove ZydisPE by @athre0z in [#257](https://github.com/zyantific/zydis/pull/257) * Docs: add man pages by @Tachi107 in [#267](https://github.com/zyantific/zydis/pull/267) * Registers: add lookup tables for `ZydisRegister` and `ZydisRegisterClass` by @flobernd in [#283](https://github.com/zyantific/zydis/pull/283) * Tools: improve `ZydisInfo` by @flobernd in [#285](https://github.com/zyantific/zydis/pull/285) * Formatter: fix `MASM` style disassembly by @flobernd in [#298](https://github.com/zyantific/zydis/pull/298) * Segments: move segment functions into a separate, optional header by @athre0z in [#348](https://github.com/zyantific/zydis/pull/348) * Formatter: simplify formatter interface by @athre0z in [#361](https://github.com/zyantific/zydis/pull/361) * Doc: switch Doxygen theme by @athre0z in [#373](https://github.com/zyantific/zydis/pull/373) * CI: add automated documentation builds by @athre0z in [#374](https://github.com/zyantific/zydis/pull/374) **Full Changelog**: https://github.com/zyantific/zydis/compare/v3.2.1...v4.0.0 2022-11-20T17:10:10+00:00